Double bootstrapped clock buffer circuit

ABSTRACT

A buffer circuit has first and second boot-strap circuits. The first boot-strap circuit charges the gate of an output MOS transistor to a voltage above a supply voltage when an input signal has a first logic level. The gate of a precharging MOS transistor in the first boot-strap circuit is driven by the second boot-strap circuit so as to precharge a capacitor in the first boot-strap circuit to a voltage above the supply voltage when the input signal has a second logic level.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a buffer circuit for amplifying input signals such as clock signals.

2. Description of the Prior Art

A known buffer circuit used in integrated semiconductor circuits, e.g., in a clock generator in memory devices, charges the gate of an output metal oxide semiconductor (MOS) transistor to a voltage above a supply voltage V_(CC) so that an output signal OUT thereof rises rapidly to a voltage equal to V_(CC).

A boot-strap circuit is in general provided in such a buffer circuit to charge the gate of the output MOS transistor to the high voltage. The boot-strap circuit in the buffer circuit according to prior art, however, does not have sufficient charging capacity.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an improved buffer circuit with an increased reset efficiency and a faster rising output signal.

The above object is achieved by a buffer circuit which includes: first and second output MOS transistors connected in series between a supply voltage and ground; an output terminal connected between the first and second output MOS transistors and a first boot-strap circuit connected to the gate of the first output MOS transistor. The first boot-strap circuit charges the gate of the first output MOS transistor to a voltage above the supply voltage when an input signal has a first logic level, thus turning on the first output MOS transistor and charging the output terminal to the supply voltage. The first boot-strap circuit includes a capacitor and a MOS transistor which precharges the capacitor. Also included in the buffer circuit is a second boot-strap circuit having an output node connected to the gate of the precharging MOS transistor in the first boot-strap circuit, for driving the gate of the precharging MOS transistor to a precharged voltage above the supply voltage when the input signal is a second logic level.

According to the present invention as described above, since the gate of the precharging MOS transistor in the first boot-strap circuit is driven by the second boot-strap circuit to precharge the capacitor in the first boot-strap circuit to a voltage above the supply voltage during a certain time, the reset efficiency of the buffer circuit can be increased and the rising speed of the output signal can be increased. Furthermore, according to the present invention, these effects can be obtained by just adding a simple circuit to the prior buffer circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other related objects and features of the present invention will be apparent from the description of the present invention set forth below, with reference to the accompanying drawings, wherein:

FIG. 1 is a circuit diagram of an embodiment of the present invention;

FIG. 2 is a waveform diagram for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is a circuit diagram of another embodiment of the present invention; and

FIG. 4 is a waveform diagram for explaining the operation of the embodiment of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 which illustrates an embodiment of the present invention, reference symbol BST₁ indicates a first boot-strap circuit and BST₂ indicates a second boot-strap circuit which is added according to the present invention.

First, the operation of a conventional buffer circuit without the second boot-strap circuit BST₂ and, thus, with the gate of transistor Q₁ directly connected to the supply voltage V_(CC) will be discribed. In FIG. 1, Q₁₀ to Q₁₂ indicate depletion-mode MOS transistors and Q₁ to Q₄ and Q₁₃ to Q₁₉ indicate enhancement-mode MOS transistors. The MOS transistor Q₁ and a capacitor C₂ comprise the first boot-strap circuit BST₁.

When an input signal IN applied to the gate of the MOS transistor Q₁₃ rises from a low logic level to a high logic level, the MOS transistor Q₁₃ turns on and, thus, node N₁ is discharged to a low logic level as shown in FIG. 2. As a result, the MOS transistor Q₁₄ turns off and node N₂ is pulled up to V_(CC) by the MOS transistor Q₁₁, causing the MOS transistors Q₁₅ to Q₁₇ to turn on. As the MOS transistor Q₁₆ turns on, node N₆ is discharged to a low logic level or ground V_(SS). Also, as the MOS transistor Q₁₇ turns on, the output terminal OUT is discharged to ground V_(SS). Furthermore, since the MOS transistor Q₁₅ turns on, current flows from V_(CC) to V_(SS) via Q₁ --N₄ --Q₁₂ --N₅ --Q₁₅ --N₁ --Q₁₃, which causes node N₅ to be discharged to a low logic level and the MOS transistors Q₁₈ and Q₁₉ to turn off.

Node N₄ is boot-strapped by the capacitor C₂ to a voltage above V_(CC) when the MOS transistor Q₁₆ is off, namely when the input signal IN has a low logic level. When the MOS transistor Q₁₆ turns on, node N₄ is lowered to a voltage equal to the supply voltage V_(CC) minus one threshold voltage V_(th) of the MOS transistor Q₁. The capacitor C₂ is precharged during the turning on of Q₁₆. A broken line N₄ ' in FIG. 2 shows the voltage at node N₄ according to the above-described conventional circuit. Since node N₄ is below V_(CC) by the amount of the threshold voltage Vth when the input signal IN has the high logic level, node N₅ is not charged to a sufficiently high voltage by the capacitor C₂ via the boot-strapping node N₄ when the input signal IN falls to a low logic level. At this time (low IN signal) node N₁ is charged to a high logic level, node N₂ is discharged to a low logic level, the transistor Q₁₄ turns on, and the transistors Q₁₅ to Q₁₇ turn off, causing the voltage at node N₆ to increase. A broken line N₅ ' shown in FIG. 2 shows the voltage at node N₅. The voltage N₅ ' at node N₅ causes the MOS transistor 19 to turn on. If the voltage N₅ ' at node N₅ is not sufficiently high, although the voltage N₅ ' is higher than V_(CC), the output signal OUT will not increase to V_(CC) or it will take a lot of time to increase the output signal to V_(CC).

Hereinafter, the operation of the buffer circuit according to the embodiment illustrated in FIG. 1 will be described. The present invention is intended to sufficiently increase the voltage at node N₄ during the period when the input signal IN has a high logic level, hereinafter called the "reset period". In order to perform this operation, this embodiment of the present invention provides the second boot-strap circuit BST₂, whose output node N₃ is connected to the gate of the MOS transistor Q₁. A boot-strapping capacitor C₁ in the second boot-strap circuit BST₂ is connected between node N₂ and the output node N₃. It should be noted that node N₂ is maintained at a high logic level during the reset period. Thus, during the reset period, the gate of the MOS transistor Q₁ (node N₃) is charged to a voltage above V_(CC) via the capacitor C₁, causing node N₄ to be charged to a voltage below but near V_(CC) via the transistor Q₁ during the reset period, as shown by a solid line N₄ in FIG. 2.

When the input signal IN falls to a low logic level from a high logic level, the voltage at node N₂ changes from a high logic level to a low logic level and thus node N₃ is discharged to a voltage below V_(CC), causing the transistor Q₁ to turn off. At the same time, the MOS transistor Q₁₆ turns off, causing the voltage at node N₆ to increase. As a result, node N₄ is boot-strapped via the capacitor C₂ to a voltage above V_(CC), and thus node N₅ is charged to a voltage above V_(CC), as shown by the solid line N₅ in FIG. 2. This charged voltage at node N₅ is sufficiently high to drive the MOS transistors Q₁₈ and Q₁₉ and to rapidly raise the output signal OUT to V_(CC). The MOS transistor Q₁ is in the on-state to cause the charging of capacitor C₂ via V_(CC) --Q₁ --N₄ --C₂ --Q₁₆ --V_(SS) when the voltage at node N₃ is above V_(CC). When the transistor Q₁₄ turns on the voltage at N₂ drops and the transistor Q₁₆ turns off, thus as N₃ becomes ≦V_(CC) and N₄ becomes <V_(CC), the MOS transistor Q₁ turns off, whereby node N₄ is prevented from being discharged to V_(CC).

Besides the boot-strapping capacitor C₁ and the enhancement-mode MOS transistor Q₂ connected as a diode for precharging the capacitor C₁, the second boot-strap circuit BST₂ preferably includes the enhancement-mode MOS transistor Q₃ connected as a diode between node N₃ and V_(CC). The transistor Q₃, whose drain and gate are connected to node N₃ and whose source is connected to V_(CC), prevents node N₃ from being over-charged. In other words transistor Q₃ clamps node N₃ to a voltage which is higher than V_(CC) by a predetermined voltage. As a result, if V_(CC) decreases when the output signal OUT rises, since the maximum voltage at node N₃ decreases depending upon V_(CC), the transistor Q₁ will not turn on, causing node N₄ not to discharge to V_(CC).

In addition, the second boot-strap circuit BST₂ preferably includes the MOS transistor Q₄, which is connected between node N₃ and V_(CC) and controlled by the voltage at node N₄. This transistor Q₄ prevents node N₄ from being over-charged and also ensures cutting off operation of the transistor Q₁. The transistor Q₁ should be cut off during a period when the voltage at node N₄ is above V_(CC). Therefore, if the transistor Q₄ is conductive during this period, the voltage at node N₃ is clamped to V_(CC). As a result, the transistor Q₁ will remain turned off even if V_(CC) drops.

FIG. 3 illustrates another embodiment of the present invention. In this embodiment, the drain of the MOS transistor Q₁₄ is connected to node N₄ and furthermore to the gates of the transistors Q₁₈ and Q₁₉. The boot-strapping capacitor C₁ in the second boot-strap circuit BST₂ is connected between node N₄ and node N₃. The drain (node N₅) of the MOS transistor Q₂₅ is connected to the gates of the MOS transistors Q₁₆ and Q₁₇. Node N₅ is also connected via the MOS transistor Q₁₂ to node N₃. The remainder of this embodiment is essentially the same as that of the embodiment of FIG. 1.

Hereinafter the operation of the buffer circuit according to the embodiment of FIG. 3 will be described. When the input signal IN rises to a high logic level from a low logic level, the MOS transistor Q₁₃ turns on and thus node N₁ is gradually discharged to V_(SS) as shown in FIG. 4. As a result, the MOS transistor Q₁₄ turns off and thus node N₄ is charged via Q₁₄ causing the voltage at node N₃ to be boot-strapped by the capacitor C₁ to a voltage well above the supply voltage V_(CC) as shown in FIG. 4. Therefore, the MOS transistor Q₁ is maintained in the on-state and node N₄ is charged nearly to V_(CC). When node N₄ is charged to a voltage equal to the voltage at node N₁ plus one threshold voltage V_(th), the MOS transistor Q₂₅ turns on causing node N₅ to be discharged as shown in FIG. 4. Thus the enhancement-type MOS transistor Q₂₂ also turns on causing node N₃ to rapidly discharge. Accordingly, the MOS transistors Q₁, Q₁₆ and Q₁₇ turn off. Since, in this case, the MOS transistor Q₁₈ is in the on-state, node N₆ is boot-strapped to a voltage near to V_(CC). As a pulse-shaped voltage produced by boot-strapping is applied to node N₄ via the capacitor C₂, node N₄ is boot-strapped to a voltage well above V_(CC). This charged voltage at node N₄ is sufficiently high to drive the MOS transistors Q₁₈ and Q₁₉ and to rapidly raise the output signal OUT to V_(CC). Since the MOS transistor Q₁ is in off-state in this case, node N₄ can be prevented from being discharged to V_(CC).

Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims. 

I claim:
 1. A buffer circuit, operatively connected to a supply voltage and to receive an input signal, producing an output signal in response to the input signal, comprising:first and second output transistors having their drain-source current paths operatively connected in series between the supply voltage and ground, thereby forming a junction between said first and second output transistors, each of said first and second output transistors having a gate; an output terminal operatively connected to the junction between said first and second output transistors; a first boot-strap circuit operatively connected to the gate of said first output transistor for charging the gate of said first output transistor to a charged voltage above the supply voltage when the input signal has a first logic level, turning on said first output transistor and charging said output terminal to the supply voltage, said first boot-strap circuit comprising: a capacitor operatively connected to the gate of said first output transistor; and a precharging transistor, having its drain-source current path coupled between the supply voltage and saidcapacitor, for precharging said capacitor and having a gate; and a second boot-strap circuit having an output node operatively connected to the gate of said precharging transistor in said first boot-strap circuit, for driving the gate of said precharging transistor to a precharged voltage above the supply voltage when the input signal has a second logic level.
 2. A buffer circuit as claimed in claim 1, wherein said second boot-strap circuit comprises a capacitor, operatively connected to the output node, which is precharged when the input signal has the first logic level.
 3. A buffer circuit as claimed in claim 1, wherein said second boot-strap circuit further comprises diode means, operatively connected to the supply voltage and the output node, for clamping the output node to a precharge voltage which is higher than the supply voltage by a predetermined voltage.
 4. A buffer circuit as claimed in claim 3, wherein said diode means comprises a clamping transistor having a gate and a drain operatively connected to the output node and a source operatively connected to the supply voltage.
 5. A buffer circuit as claimed in claim 1,wherein said first boot-strap circuit further comprises a junction node between said precharging transistor and said capacitor, and wherein said second boot-strap circuit comprises clamping means operatively connected to the supply voltage and the junction node, for maintaining the output node at the supply voltage when the junction node between said precharging transistor and said capacitor in said first boot-strap circuit is above the supply voltage.
 6. A buffer circuit as claimed in claim 5, wherein said clamping means comprises a clamping transistor having a source operatively connected to the output node, a drain operatively connected to the supply voltage and a gate operatively connected to the junction node. 